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1 msps, 12-bit impedance converter, network analyzer ad5933 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2010 analog devices, inc. all rights reserved. features programmable output peak-to-peak excitation voltage to a maximum frequency of 100 khz programmable frequency sweep capability with serial i 2 c interface frequency resolution of 27 bits (<0.1 hz) impedance measurement range from 1 k to 10 m capable of measuring of 100 to 1 k with additional circuitry internal temperature sensor (2c) internal system clock option phase measurement capability system accuracy of 0.5% 2.7 v to 5.5 v power supply operation temperature range: ?40c to +125c 16-lead ssop package applications electrochemical analysis bioelectrical impedance analysis impedance spectroscopy complex impedance measurement corrosion monitoring and protection equipment biomedical and automotive sensors proximity sensing nondestructive testing material property analysis fuel/battery cell condition monitoring general description the ad5933 is a high precision impedance converter system solution that combines an on-board frequency generator with a 12-bit, 1 msps, analog-to-digital converter (adc). the frequency generator allows an external complex impedance to be excited with a known frequency. the response signal from the impedance is sampled by the on-board adc and a discrete fourier transform (dft) is processed by an on-board dsp engine. the dft algorithm returns a real (r) and imaginary (i) data-word at each output frequency. once calibrated, the magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated. this is done off chip using the real and imaginary register contents, which can be read from the serial i 2 c interface. a similar device, also available from analog devices, inc., is the ad5934 , a 2.7 v to 5.5 v, 250 ksps, 12-bit impedance converter, with an internal temperature sensor and is packaged in a 16- lead ssop. functional block diagram vdd/2 dac z( ) scl sda dvdd a v dd mclk agnd dgnd r out vout ad5933 rfb vin 05324-001 1024-point dft i 2 c interface imaginary register real register oscillator dds core (27 bits) temperature sensor adc (12 bits) lpf gain figure 1.
ad5933 rev. c | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 i 2 c serial interface timing characteristics .............................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and descriptions .............................................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 12 system description ......................................................................... 13 transmit stage ............................................................................. 14 frequency sweep command sequence ................................... 15 receive stage ............................................................................... 15 dft operation ........................................................................... 15 system clock ............................................................................... 16 temperature sensor ................................................................... 16 temperature conversion details .............................................. 16 temperature value register ...................................................... 16 temperature conversion formula ........................................... 16 impedance calculation .................................................................. 17 magnitude calculation .............................................................. 17 gain factor calculation ............................................................ 17 impedance calculation using gain factor ............................. 17 gain factor variation with frequency .................................... 17 two-point calibration ............................................................... 18 two-point gain factor calculation ......................................... 18 gain factor setup configuration ............................................. 18 gain factor recalculation ......................................................... 18 gain factor temperature variation ......................................... 19 impedance error ......................................................................... 19 measuring the phase across an impedance ........................... 21 performing a frequency sweep .................................................... 23 register map .................................................................................... 24 control register (register address 0x80, register address 0x81) ............................................................................................. 24 start frequency register (register address 0x82, register address 0x83, register address 0x84)..................................... 25 frequency increment register (register address 0x85, register address 0x86, register address 0x87) ..................... 26 number of increments register (register address 0x88, register address 0x89) .............................................................. 26 number of settling time cycles register (register address 0x8a, register address 0x8b) ................................................. 26 status register (register address 0x8f) .................................. 27 temperature data register (16 bitsregister address 0x92, register address 0x93) .............................................................. 27 real and imaginary data registers (16 bitsregister address 0x94, register address 0x95, register address 0x96, register address 0x97) .............................................................. 27 serial bus interface ......................................................................... 28 general i 2 c timing .................................................................... 28 writing/reading to the ad5933 .............................................. 29 block write .................................................................................. 29 read operations ......................................................................... 30 typical applications ....................................................................... 31 measuring small impedances ................................................... 31 biomedical: noninvasive blood impedance measurement .. 33 sensor/complex impedance measurement ............................ 33 electro-impedance spectroscopy............................................. 34 choosing a reference for the ad5933 ........................................ 35 layout and configuration ............................................................. 36 power supply bypassing and grounding ................................ 36 evaluation board ............................................................................ 37 using the evaluation board ...................................................... 37 prototyping area ........................................................................ 37 crystal oscillator (xo) vs. external clock ............................. 37 schematics ................................................................................... 38 bill of materials ........................................................................... 42 outline dimensions ....................................................................... 43 ordering guide .......................................................................... 43
ad5933 rev. c | page 3 of 44 revision history 8/10rev. b to rev. c changes to impedance error section ........................................... 19 changes to figure 45 ...................................................................... 38 changes to u4 description in table 19 ........................................ 42 2/10rev. a to rev. b changes to general description ..................................................... 1 5/08rev. 0 to rev. a changes to layout .............................................................. universal changes to figure 1 ........................................................................... 1 changes to table 1 ............................................................................ 4 changes to figure 17 ...................................................................... 13 changes to system description section ...................................... 13 changes to figure 19 ...................................................................... 14 changes to figure 24 ...................................................................... 18 changes to impedance error section ........................................... 19 added measuring the phase across an impedance section ..... 21 changes to register map section ................................................. 24 added measuring small impedances section ............................. 31 changes to table 18 ........................................................................ 35 added evaluation board section .................................................. 37 changes to ordering guide ........................................................... 43 9/05revision 0: initial version
ad5933 rev. c | page 4 of 44 specifications vdd = 3.3 v, mclk = 16.776 mhz, 2 v p-p output excitation voltag e @ 30 khz, 200 k connected between pin 5 and pin 6; feedback resistor = 200 k connected between pin 4 and pin 5; pga gain = 1, unless otherwise noted. table 1. parameter y version 1 unit test conditions/comments min typ max system impedance range 1 k 10 m 100 to 1 k requires extra buffer circuitry, see the measuring small impedances section total system accuracy 0.5 % 2 v p-p output excitation voltage at 30 khz, 200 k connected between pin 5 and pin 6 system impedance error drift 30 ppm/c transmit stage output frequency range 2 1 100 khz output frequency resolution 0.1 hz <0.1 hz resolution achievable using dds techniques mclk frequency 16.776 mhz ma ximum system clock frequency internal oscillator frequency 3 16.776 mhz frequency of internal clock internal oscillator temperature coefficient 30 ppm/c transmit output voltage range 1 ac output excitation voltage 4 1.98 v p-p see figure 4 for output voltage distribution dc bias 5 1.48 v dc bias of the ac excitation signal; see figure 5 dc output impedance 200 t a = 25c short-circuit current to ground at vout 5.8 ma t a = 25c range 2 ac output excitation voltage 4 0.97 v p-p see figure 6 dc bias 5 0.76 v dc bias of output excitation signal; see figure 7 dc output impedance 2.4 k short-circuit current to ground at vout 0.25 ma range 3 ac output excitation voltage 4 0.383 v p-p see figure 8 dc bias 5 0.31 v dc bias of output excitation signal; see figure 9 dc output impedance 1 k short-circuit current to ground at vout 0.20 ma range 4 ac output excitation voltage 4 0.198 v p-p see figure 10 dc bias 5 0.173 v dc bias of output excitation signal. see figure 11 dc output impedance 600 short-circuit current to ground at vout 0.15 ma system ac characteristics signal-to-noise ratio 60 db total harmonic distortion ?52 db spurious-free dynamic range wide band (0 mhz to 1 mhz) ?56 db narrow band (5 khz) ?85 db
ad5933 rev. c | page 5 of 44 parameter y version 1 unit test conditions/comments min typ max receive stage input leakage current 1 na to vin pin input capacitance 6 0.01 pf pin capacitance between vin and gnd feedback capacitance (c fb ) 3 pf feedback capacitance around current- to-voltage amplifier; appears in parallel with feedback resistor analog-to-digital converter 6 resolution 12 bits sampling rate 250 ksps adc throughput rate temperature sensor accuracy 2.0 c ?40c to +125c temperature range resolution 0.03 c temperature conversion time 800 s conversion time of single temperature measurement logic inputs input high voltage (v ih ) 0.7 vdd input low voltage (v il ) 0.3 vdd input current 7 1 a t a = 25c input capacitance 7 pf t a = 25c power requirements vdd 2.7 5.5 v idd (normal mode ) 10 15 ma vdd = 3.3 v 17 25 ma vdd = 5.5 v idd (standby mode) 11 ma vdd = 3.3 v; see the control register (register address 0x80, register address 0x81) section 16 ma vdd = 5.5 v idd (power-down mode) 0.7 5 a vdd = 3.3 v 1 8 a vdd = 5.5 v 1 temperature range for y version = ? 40c to +125c, typical at 25c. 2 the lower limit of the output excitation frequency ca n be lowered by scaling the clock supplied to the ad5933. 3 refer to figure 14, figure 15, and figure 16 for the inte rnal oscillator frequency dist ribution with temperature. 4 the peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula: output excitation voltage (v p-p) = [2/3.3] vdd where vdd is the supply voltage. 5 the dc bias value of the output excitation voltage scales with supply voltage according to the following formula: output excitation bias voltage (v) = [2/3.3] vdd where vdd is the supply voltage. 6 guaranteed by design or characterization, not production tested . input capacitance at the vout pin is equal to pin capacitance divided by open-loop gain of current- to-voltage amplifier. 7 the accumulation of the currents into pin 8, pin 15, and pin 16.
ad5933 rev. c | page 6 of 44 i 2 c serial interface timing characteristics vdd = 2.7 v to 5.5 v. all specifications t min to t max , unless otherwise noted. 1 table 2. parameter 2 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd, sta , start/repeated start condition hold time t 5 100 ns min t su, dat , data setup time t 6 3 0.9 s max t hd, dat , data hold time 0 s min t hd, dat , data hold time t 7 0.6 s min t su, sta , setup time for repeated start t 8 0.6 s min t su, sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t f , rise time of sda when transmitting 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 300 ns max t f , fall time of scl and sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 250 ns max t f , fall time of sda when receiving 20 + 0.1 c b 4 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line 1 see figure 2. 2 guaranteed by design and characterization, not production tested. 3 a master device must provide a hold time of at least 300 ns fo r the sda signal (referred to v ih min of the scl signal) to bridge the undefined falling edge of scl. 4 c b is the total capacitance of one bus line in picofarads. note that t r and t f are measured between 0.3 vdd and 0.7 vdd. scl s da t 9 t 3 t 10 t 11 t 4 t 4 t 6 t 2 t 5 t 7 t 8 t 1 05324-002 start condition repeated start condition stop condition figure 2. i 2 c interface timing diagram
ad5933 rev. c | page 7 of 44 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating dvdd to gnd ?0.3 v to +7.0 v avdd1 to gnd ?0.3 v to +7.0 v avdd2 to gnd ?0.3 v to +7.0 v sda/scl to gnd ?0.3 v to vdd + 0.3 v vout to gnd ?0.3 v to vdd + 0.3 v vin to gnd ?0.3 v to vdd + 0.3 v mclk to gnd ?0.3 v to vdd + 0.3 v operating temperature range extended industrial (y grade) ?40c to +125c storage temperature range ?65c to +160c maximum junction temperature 150c ssop package, thermal impedance ja 139c/w jc 136c/w reflow soldering (pb-free) peak temperature 260c time at peak temperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5933 rev. c | page 8 of 44 pin configuration and descriptions nc 1 nc 2 nc 3 rfb 4 scl 16 sda 15 agnd2 14 agnd1 13 vin 5 vout 6 nc 7 dgnd 12 avdd2 11 avdd1 10 mclk 8 dvdd 9 nc = no connect ad5933 top view (not to scale) 05324-003 it is recommended to tie all supply connections (pin 9, pin 10, and pin 11) and run from a single supply between 2.7v and 5.5v. it is also recommended to connect all ground signals together (pin 12, pin 13, and pin 14). notes: 1. figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1, 2, 3, 7 nc no connect. 4 rfb external feedback resistor. connected from pin 4 to pin 5 and used to set the gain of the current-to-voltage amplifier on the receive side. 5 vin input to receive transimpedance amplifier. presents a virtual earth voltage of vdd/2. 6 vout excitation voltage signal output. 8 mclk the master clock for the sy stem is supplied by the user. 9 dvdd digital supply voltage. 10 avdd1 analog supply voltage 1. 11 avdd2 analog supply voltage 2. 12 dgnd digital ground. 13 agnd1 analog ground 1. 14 agnd2 analog ground 2. 15 sda i 2 c data input. open-drain pins requiring 10 k pull-up resistors to vdd. 16 scl i 2 c clock input. open-drain pins requiring 10 k pull-up resistors to vdd.
ad5933 rev. c | page 9 of 44 typical performance characteristics 35 0 number of devices 30 25 20 15 10 5 2.06 voltage (v) 1.92 1.94 1.96 1.98 2.00 2.02 2.04 mean = 1.9824 sigma = 0.0072 05324-004 0.68 0.86 voltage (v) 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 mean = 0.7543 sigma = 0.0099 30 0 number of devices 25 20 15 10 5 05324-007 figure 4. range 1 output excitation voltage distribution, vdd = 3.3 v figure 7. range 2 dc bias distribution, vdd = 3.3 v 1.30 1.75 voltage (v) 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 mean = 1.4807 sigma = 0.0252 0 number of devices 30 25 20 15 10 5 05324-005 30 0 0.370 0.400 voltage (v) number of devices 25 20 15 10 5 0.375 0.380 0.385 0.390 0.395 mean = 0.3827 sigma = 0.00167 05324-008 figure 5. range 1 dc bias distribution, vdd = 3.3 v figure 8. range 3 output excitation voltage distribution, vdd = 3.3 v 30 0 number of devices 25 20 15 10 5 voltage (v) 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 mean = 0.9862 sigma = 0.0041 05324-006 0.290 0.320 voltage (v) 0.295 0.300 0.305 0.310 0.315 mean = 0.3092 sigma = 0.0014 30 0 number of devices 25 20 15 10 5 05324-009 figure 6. range 2 output excitation voltage distribution, vdd = 3.3 v figure 9. range 3 dc bias distribution, vdd = 3.3 v
ad5933 rev. c | page 10 of 44 voltage (v) 0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206 mean = 0.1982 sigma = 0.0008 30 0 number of devices 25 20 15 10 5 05324-010 figure 10. range 4 output excitation voltage distribution, vdd = 3.3 v 0.160 0.205 voltage (v) 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 mean = 0.1792 sigma = 0.0024 30 0 number of devices 25 20 15 10 5 05324-011 figure 11. range 4 dc bias distribution, vdd = 3.3 v 15.8 10.8 0 18 mclk frequency (mhz) idd (ma) 15.3 14.8 14.3 13.8 13.3 12.8 12.3 11.8 11.3 avdd1, avdd2, dvdd connected together. output excitation frequency = 30khz rfb, z calibration = 100k ? 246810121416 05324-012 figure 12. typical supply current vs. mclk frequency 0.4 ?1.0 0 400 phase (degrees) phase error (degrees) 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 50 100 150 200 250 300 350 vdd = 3.3v t a = 25c f = 32khz 05324-013 figure 13. typical phase error
ad5933 rev. c | page 11 of 44 16.4 16.6 16.8 17.0 17.2 oscillator frequency (mhz) count 05324-014 0 2 4 6 8 10 12 n = 106 mean = 16.8292 sd = 0.142904 temp = ?40c 16.4 16.6 16.8 17.0 17.2 oscillator frequency (mhz) count 05324-016 0 2 4 6 8 10 12 n = 100 mean = 16.7257 sd = 0.137633 temp = 125c figure 14. frequency distribution of internal oscillator at ?40c figure 16. frequency distribution of internal oscillator at 125c 16 0 2 4 6 8 10 12 14 16.4 16.6 16.8 17.0 17.2 oscillator frequency (mhz) count 05324-015 n = 100 mean = 16.7811 sd = 0.0881565 temp = 25c figure 15. frequency distribution of internal oscillator at 25c
ad5933 rev. c | page 12 of 44 terminology tot a l sys te m ac c u r a c y the ad5933 can accurately measure a range of impedance values to less than 0.5% of the correct impedance value for supply voltages between 2.7 v to 5.5 v. spurious-free dynamic range (sfdr) along with the frequency of interest, harmonics of the funda- mental frequency and images of these frequencies are present at the output of a dds device. the spurious-free dynamic range refers to the largest spur or harmonic present in the band of interest. the wideband sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 hz to nyquist bandwidth. the narrow-band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz, about the fundamental frequency. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the funda- mental, where v1 is the rms amplitude of the fundamental and v2, v3, v4, v5, and v6 are the rms amplitudes of the second through the sixth harmonics. for the ad5933, thd is defined as v1 v6vv4v3v2 thd 22222 5 log20(db) +++ =
ad5933 rev. c | page 13 of 44 system description adc (12 bits) vdd/2 dds core (27 bits) dac z( ) i 2 c interface imaginary register real register mac core (1024 dft) lpf scl sda mclk r out vout ad5933 rfb vin programmable gain amplifier 5 1 windowing of data cos sin microcontroller mclk 05324-017 temperature sensor oscillator figure 17. block overview the ad5933 is a high precision impedance converter system solution that combines an on-board frequency generator with a 12-bit, 1 msps adc. the frequency generator allows an external complex impedance to be excited with a known frequency. the response signal from the impedance is sampled by the on-board adc and dft processed by an on-board dsp engine. the dft algorithm returns both a real (r) and imaginary (i) data-word at each frequency point along the sweep. the impedance magnitude and phase are easily calculated using the following equations: 22 ir magnitude phase = tan ?1 ( i / r ) to characterize an impedance profile z( z ), generally a frequency sweep is required, like that shown in figure 18 . frequency impedance 05324-018 figure 18. impedance vs. frequency profile the ad5933 permits the user to perform a frequency sweep with a user-defined start frequency, frequency resolution, and number of points in the sweep. in addition, the device allows the user to program the peak-to-peak value of the output sinusoidal signal as an excitation to the external unknown impedance connected between the vout and vin pins. table 5 gives the four possible output peak-to-peak voltages and the corresponding dc bias levels for each range for 3.3 v. these values are ratiometric with vdd. so for a 5 v supply ppv3 3.3 0.5 98.1 u 1rangeforvoltage excitation output ppv24.2 3.3 0.5 48.1 u 1rangeforvoltagebiasdcoutput table 5. voltage levels respective bias levels for 3.3 v range output excitation voltage amplitude output dc bias level 1 1.98 v p-p 1.48 v 2 0.97 v p-p 0.76 v 3 383 mv p-p 0.31 v 4 198 mv p-p 0.173 v the excitation signal for the transmit stage is provided on-chip using dds techniques that permit subhertz resolution. the receive stage receives the input signal current from the unknown impedance, performs signal processing, and digitizes the result. the clock for the dds is generated from either an external reference clock, which is provided by the user at mclk, or by the internal oscillator. the clock for the dds is determined by the status of bit d3 in the control register (see register address 0x81 in the register map section).
ad5933 rev. c | page 14 of 44 transmit stage as shown in figure 19 , the transmit stage of the ad5933 is made up of a 27-bit phase accumulator dds core that provides the output excitation signal at a particular frequency. the input to the phase accumulator is taken from the contents of the start frequency register (see register address 0x82, register address 0x83, and register address 0x84). although the phase accumu- lator offers 27 bits of resolution, the start frequency register has the three most significant bits (msbs) set to 0 internally; therefore, the user has the ability to program only the lower 24 bits of the start frequency register. phase accumulator (27 bits) vout dac r(gain) v bias 0 5324-019 figure 19. transmit stage the ad5933 offers a frequency resolution programmable by the user down to 0.1 hz. the frequency resolution is programmed via a 24-bit word loaded serially over the i 2 c interface to the frequency increment register. the frequency sweep is fully described by the programming of three parameters: the start frequency, the frequency increment, and the number of increments. start frequency this is a 24-bit word that is programmed to the on-board ram at register address 0x82, register address 0x83, and register address 0x84 (see the register map section). the required code loaded to the start frequency register is the result of the formula shown in equation 1, based on the master clock frequency and the required start frequency output from the dds. 27 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = (1) for example, if the user requires the sweep to begin at 30 khz and has a 16 mhz clock signal connected to mclk, the code that needs to be programmed is given by 0x0f5c28 2 4 mhz16 khz30 27 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = the user programs the value of 0x0f to register address 0x82, the value of 0x5c to register addres s 0x83, and the value of 0x28 to register address 0x84. frequency increment this is a 24-bit word that is programmed to the on-board ram at register address 0x85, register address 0x86, and register address 0x87 (see the register map ). the required code loaded to the frequency increment register is the result of the formula shown in equation 2, based on the master clock frequency and the required increment frequency output from the dds. 27 2 4 re ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = (2) for example, if the user requires the sweep to have a resolution of 10 hz and has a 16 mhz clock signal connected to mclk, the code that needs to be programmed is given by 0x00014f 4 mhz16 hz10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = the user programs the value of 0x00 to register address 0x85, the value of 0x01 to register address 0x86, and the value of 0x4f to register address 0x87. number of increments this is a 9-bit word that represents the number of frequency points in the sweep. the number is programmed to the on-board ram at register address 0x88 and register address 0x89 (see the register map section). the maximum number of points that can be programmed is 511. for example, if the sweep needs 150 points, the user programs the value of 0x00 to register address 0x88 and the value of 0x96 to register address 0x89. once the three parameter values have been programmed, the sweep is initiated by issuing a start frequency sweep command to the control register at register address 0x80 and register address 0x81 (see the register map section). bit d2 in the status register (register address 0x8f) indicates the completion of the frequency measurement for each sweep point. incrementing to the next frequency sweep point is under the control of the user. the measured result is stored in the two register groups that follow: 0x94, 0x95 (real data) and 0x96, 0x97 (imaginary data) that should be read before issuing an increment frequency command to the control register to move to the next sweep point. there is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register . this has the benefit of allowing the user to average successive readings. when the frequency sweep has completed all frequency points, bit d3 in the status register is set, indicating completion of the sweep . once this bit is set, further increments are disabled.
ad5933 rev. c | page 15 of 44 frequency sweep command sequence receive stage the following sequence must be followed to implement a frequency sweep: the receive stage comprises a current-to-voltage amplifier, followed by a programmable gain amplifier (pga), antialiasing filter, and adc. the receive stage schematic is shown in figure 20 . the unknown impedance is connected between the vout and vin pins. the first stage current-to-voltage amplifier configuration means that a voltage present at the vin pin is a virtual ground with a dc value set at vdd/2. the signal current that is developed across the unknown impedance flows into the vin pin and develops a voltage signal at the output of the current- to-voltage converter. the gain of the current-to voltage amplifier is determined by a user-selectable feedback resistor connected between pin 4 (rfb) and pin 5 (vin). it is important for the user to choose a feedback resistance value that, in conjunction with the selected gain of the pga stage, maintains the signal within the linear range of the adc (0 v to vdd). 1. enter standby mode. prior to issuing a start frequency sweep command, the device must be placed in a standby mode by issuing an enter standby mode command to the control register (register address 0x80 and register address 0x81). in this mode, the vout and vin pins are connected internally to ground so there is no dc bias across the external impedance or between the impedance and ground. 2. enter initialize mode. in general, high q complex circuits require a long time to reach steady state. to facilitate the measurement of such impedances, this mode allows the user full control of the settling time requirement before entering start frequency sweep mode where the impedance measurement takes place. the pga allows the user to gain the output of the current-to- voltage amplifier by a factor of 5 or 1, depending upon the status of bit d8 in the control register (see the register map section, register address 0x80). the signal is then low-pass filtered and presented to the input of the 12-bit, 1 msps adc. an initialize with a start frequency command to the control register enters initialize mode. in this mode the impedance is excited with the programmed start frequency, but no meas- urement takes place. the user times out the required settling time before issuing a start frequency sweep command to the control register to enter the start frequency sweep mode. 5 r r r r c v in vdd/2 rfb adc lpf 05324-020 3. enter start frequency sweep mode. the user enters this mode by issuing a start frequency sweep command to the control register. in this mode, the adc starts measuring after the programmed number of settling time cycles has elapsed. the user can program an integer number of output frequency cycles (settling time cycles) to register address 0x8a and register address 0x8b before beginning the measurement at each frequency point (see figure 34 ). figure 20. receive stage the digital data from the adc is passed directly to the dsp core of the ad5933, which performs a dft on the sampled data. the dds output signal is passed through a programmable gain stage to generate the four ranges of peak-to-peak output excitation signals listed in table 5 . the peak-to-peak output excitation volt- age is selected by setting bit d10 and bit d9 in the control register (see the control register (register address 0x80, register address 0x81) section) and is made available at the vout pin. dft operation a dft is calculated for each frequency point in the sweep. the ad5933 dft algorithm is represented by = ? = 1023 0 )))sin())(cos((()( n njnnxfx where: x(f) is the power in the signal at the frequency point f. x(n) is the adc output. cos( n ) and sin( n ) are the sampled test vectors provided by the dds core at the frequency point f. the multiplication is accumulated over 1024 samples for each frequency point. the result is stored in two, 16-bit registers representing the real and imaginary components of the result. the data is stored in twos complement format.
ad5933 rev. c | page 16 of 44 system clock the system clock for the ad5933 can be provided in one of two ways. the user can provide a highly accurate and stable system clock at the external clock pin (mclk). alternatively, the ad5933 provides an internal clock with a typical frequency of 16.776 mhz by means of an on-chip oscillator. the user can select the preferred system clock by programming bit d3 in the control register (register address 0x81, see table 11 ). the default clock option on power-up is selected to be the internal oscillator. the frequency distribution of the internal clock with temperature can be seen in figure 14 , figure 15 , and figure 16 . temperature sensor the temperature sensor is a 13-bit digital temperature sensor with a 14 th bit that acts as a sign bit. the on-chip temperature sensor allows an accurate measurement of the ambient device temper- ature to be made. the measurement range of the sensor is ?40c to +125c. at +150c, the structural integrity of the device starts to deteriorate when operated at voltage and temperature maximum specifica- tions. the accuracy within the measurement range is 2c. temperature conversion details the conversion clock for the part is internally generated; no external clock is required except when reading from and writing to the serial port. in normal mode, an internal clock oscillator runs an automatic conversion sequence. the temperature sensor block defaults to a power-down state. to perform a measurement, a measure temperature command is issued by the user to the control register (register address 0x80 and register address 0x81). after the temperature operation is complete (typically 800 s later), the block automatically powers down until the next temperature command is issued. the user can poll the status register (register address 0x8f) to see if a valid temperature conversion has taken place, indicating that valid temperature data is available to read at register address 0x92 and register address 0x93 (see the register map section). temperature value register the temperature value register is a 16-bit, read-only register that stores the temperature reading from the adc in 14-bit, twos complement format. the two msb bits are dont cares. d13 is the sign bit. the internal temperature sensor is guaranteed to a low value limit of C40c and a high va lue limit of +150c. the digital output stored in register address 0x92 and register address 0x93 for the various temperatures is outlined in tabl e 6 . the tempera- ture sensor transfer characteristic is shown in figure 21 . table 6. temperature data format temperature digital output d13d0 ?40c 11, 1011, 0000, 0000 ?30c 11, 1100, 0100, 0000 ?25c 11, 1100, 1110, 0000 ?10c 11, 1110, 1100, 0000 ?0.03125c 11, 1111, 1111, 1111 0c 00, 0000, 0000, 0000 +0.03125c 00, 0000, 0000, 0001 +10c 00, 0001, 0100, 0000 +25c 00, 0011, 0010, 0000 +50c 00, 0110, 0100, 0000 +75c 00, 1001, 0110, 0000 +100c 00, 1100, 1000, 0000 +125c 00, 1111, 1010, 0000 +150c 01, 0010, 1100, 0000 temperature conversion formula positive temperature = adc code ( d )/32 negative temperature = ( adc code ( d ) C 16384)/32 where adc code uses all 14 bits of the data byte, including the sign bit. negative temperature = ( adc code ( d ) C 8192)/32 where adc code (d ) is d13, the sign bit, and is removed from the adc code.) digital output ?40c ?0.03125c ?30c 11, 1111, 1111, 1111 11, 1100, 0100, 0000 11, 1011, 0000, 0000 temperature (c) 75c 150c 01, 0010, 1100, 0000 00, 1001, 0110, 0000 00, 0000, 0000, 0001 05324-021 figure 21. temperature sensor transfer function
ad5933 rev. c | page 17 of 44 impedance calculation magnitude calculation the first step in impedance calculation for each frequency point is to calculate the magnitude of the dft at that point. the dft magnitude is given by 22 ir magnitude += where: r is the real number stored at register address 0x94 and register address 0x95. i is the imaginary number stored at register address 0x96 and register address 0x97. for example, assume the results in the real data and imaginary data registers are as follows at a frequency point: real data register = 0x038b = 907 decimal imaginary data register = 0x0204 = 516 decimal 506.1043)516907( 2 2 =+= magnitude to convert this number into impedance, it must be multiplied by a scaling factor called the gain factor. the gain factor is calculated during the calibration of the system with a known impedance connected between the vout and vin pins. once the gain factor has been calculated, it can be used in the calculation of any unknown impedance between the vout and vin pins. gain factor calculation an example of a gain factor calculation follows, with the following assumptions: output excitation voltage = 2 v p-p calibration impedance value, z calibration = 200 k pga gain = 1 current-to-voltage amplifier gain resistor = 200 k calibration frequency = 30 khz then typical contents of the real data and imaginary data registers after a frequency point conversion are: real data register = 0xf064 = ?3996 decimal imaginary data register = 0x227e = +8830 decimal 106.9692)8830()3996( 2 2 =+?= magnitude magnitude impedance code admittance factorgain ? ? ? ? ? ? ? ? = ? ? ? ? ? ? = 1 12- 10 515.819 106.9692 k200 1 = ? ? ? ? ? ? ? ? ? ? ? ? = factorgain impedance calculation using gain factor the next example illustrates how the calculated gain factor derived previously is used to measure an unknown impedance. for this example, assume that the unknown impedance = 510 k. after measuring the unknown impedance at a frequency of 30 khz, assume that the real data and imaginary data registers contain the following data: real data register = 0xfa3f = ?1473 decimal imaginary data register = 0x0db3 = +3507 decimal 863.3802))3507()1473(( 2 2 =+?= magnitude then the measured impedance at the frequency point is given by impedance magnitude factorgain = 1 = = ? k791.509 863.3802 10819273.515 1 12 gain factor variation with frequency because the ad5933 has a finite frequency response, the gain factor also shows a variation with frequency. this variation in gain factor results in an error in the impedance calculation over a frequency range. figure 22 shows an impedance profile based on a single-point gain factor calculation. to minimize this error, the frequency sweep should be limited to as small a frequency range as possible. 101.5 98.5 54 66 frequency (khz) impedance (k ? ) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 vdd = 3.3v calibration frequency = 60khz t a = 25c measured calibration impedance = 100k ? 05324-022 figure 22. impedance profile using a single-point gain factor calculation
ad5933 rev. c | page 18 of 44 two-point calibration alternatively, it is possible to minimize this error by assuming that the frequency variation is linear and adjusting the gain factor with a two-point calibration. figure 23 shows an impedance profile based on a two-point gain factor calculation. 101.5 98.5 54 66 frequency (khz) impedance (k ? ) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 vdd = 3.3v calibration frequency = 60khz t a = 25c measured calibration impedance = 100k ? 05324-023 figure 23. impedance profile using a two-point gain factor calculation two-point gain factor calculation this is an example of a two-point gain factor calculation assuming the following: output excitation voltage = 2 v (p-p) calibration impedance value, z unknown = 100.0 k pga gain = 1 supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 100 k calibration frequencie s = 55 khz and 65 khz typical values of the gain factor calculated at the two calibration frequencies read gain factor calculated at 55 khz is 1.031224e-09 gain factor calculated at 65 khz is 1.035682e-09 difference in gain factor (gf) is 1.035682e-09 ? 1.031224e-09 = 4.458000e-12 frequency span of sweep (f) = 10 khz therefore, the gain factor required at 60 khz is given by 9- 10031224.1khz5 khz10 12-e458000.4 u u the required gain factor is 1.033453e-9. the impedance is calculated as previously described. gain factor setup configuration when calculating the gain factor, it is important that the receive stage operate in its linear region. this requires careful selection of the excitation signal range, current-to-voltage gain resistor, and pga gain. vin vdd/2 rfb adc lpf z unknown v out current-to-volt a ge gain setting resistor pga (1 or 5) 05324-024 figure 24. system voltage gain the gain through the system shown in figure 24 is given by gainpga z sistor settinggain range voltage excitation ouput unknown u u re for this example, assume the following system settings: vdd = 3.3 v gain setting resistor = 200 k z unknown = 200 k pga setting = 1 the peak-to-peak voltage presented to the adc input is 2 v p-p. however, if a pga gain of 5 was chose, the voltage would saturate the adc. gain factor recalculation t he gain factor must be recalculated for a change in any of the following parameters: x current-to-voltage gain setting resistor x output excitation voltage x pga gain
ad5933 rev. c | page 19 of 44 gain factor temperature variation the typical impedance error variation with temperature is in the order of 30 ppm/c. figure 25 shows an impedance profile with a variation in temperature for 100 k impedance using a two-point gain factor calibration. 101.5 98.5 54 66 frequency (khz) impedance (k ? ) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 +125c +25c vdd = 3.3v calibration frequency = 60khz measured calibration impedance = 100k ? 05324-025 ?40c figure 25. impedance profile variation with temperature using a two-point gain factor calibration impedance error it is important when reading the following section to note that the output impedance associated with the excitation voltages was actually measured and then cali brated out for each impedance error measurement. this was done using a keithley current source/sink and measuring the voltage. r out (for example ,200 specified for a 1.98 v p-p in the specification table) is only a typical specification and can vary from part to part. this method may not be achievable for large volume applications and in such cases, it is advised to use an extra low impedance output amplifier, as shown in figure 4 , to improve accuracy. the following are examples of the ad5933 performance when operating in the six different im pedance ranges. note that the gain factor is calculated with a precision resistor in each case. in figure 26 to figure 31 , the 10 khz excitation frequency was generated using a 4 mhz clock. minimizing the impedance range under testing also optimizes the ad5933 measurement performance. impedance range 1 (0.1 k to 1 k) the following conditions were used to conduct the test, as shown in figure 26 : output excitation voltage = 2 v p-p calibration impedance value, z calibration = 100 pga gain = 1 supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 100 7 0 10 frequency (khz) % impedance error 6 5 4 3 2 1 35 60 100 r fb = 0.1k ? calibration impedance = 100 ? t a = 25c 0.5k ? 1k ? 05324-026 figure 26. impedance range 1 typical % impedance error over frequency impedance range 2 (1 k to 10 k) the following conditions were used to conduct the test, as shown in figure 27 : output excitation voltage = 2 v p-p calibration impedance value, z calibration = 1 k pga gain = 1 supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 1 k 2.0 0 10 frequency (khz) % impedance error 35 60 100 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 r fb = 1k ? calibration impedance = 1k ? t a = 25c 5k ? 10k ? 05324-027 figure 27. impedance range 2 typical % impedance error over frequency
ad5933 rev. c | page 20 of 44 impedance range 3 (10 k to 100 k) impedance range 5 (1 m to 2 m) the following conditions were used to conduct the test, as shown in figure 28 : the following conditions were used to conduct the test, as shown in figure 30 : output excitation voltage = 2 v p-p output excitation voltage = 2 v p-p calibration impedance value, z calibration = 10 k calibration impedance value, z calibration = 100 pga gain = 1 pga gain = 1 supply voltage = 3.3 v supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 10 k current-to-voltage amplifier gain resistor = 100 k 0.3 ?0.3 10 frequency (khz) % impedance error 35 60 100 0.2 0.1 0 ?0.1 ?0.2 r fb = 10k ? calibration impedance = 10k ? t a = 25c 50k ? 100k ? 05324-028 3 ?9 10 frequency (khz) % impedance error 35 60 100 1 ?1 ?3 ?5 ?7 r fb = 1m ? calibration impedance = 100 ? t a = 25c 1.5m ? 2m ? 05324-030 figure 28. impedance range 3 typical % impedance error over frequency figure 30. impedance range 5 typical % impedance error over frequency impedance range 4 (100 k to 1 m) impedance range 6 (9 m to 10 m) the following conditions were used to conduct the test, as shown in figure 29 : the following conditions were used to conduct the test, as shown in figure 31 : output excitation voltage = 2 v p-p output excitation voltage = 2 v p-p calibration impedance value, z calibration = 100 k calibration impedance value, z calibration = 9 m pga gain = 1 pga gain = 1 supply voltage = 3.3 v supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 100 k current-to-voltage amplifier gain resistor = 9 m 1.0 ?3.5 10 frequency (khz) % impedance error 35 60 100 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 500k ? 1m ? r fb = 100k ? calibration impedance = 100k ? t a = 25c 05324-029 4 ?10 10 frequency (khz) % impedance error 2 0 ?2 ?4 ?6 ?8 35 60 100 r fb = 9m ? calibration impedance = 9m ? t a = 25c 9.5m ? 10m ? 05324-031 figure 29. impedance range 4 typical % impedance error over frequency figure 31. impedance range 6 typical % impedance error over frequency
ad5933 rev. c | page 21 of 44 measuring the phase across an impedance the ad5933 returns a complex output code made up of sepa- rate real and imaginary components. the real component is stored at register address 0x94 and register address 0x95 and the imaginary component is stored at register address 0x96 and register address 0x97 after each sweep measurement. these correspond to the real and imaginary components of the dft and not the resistive and reactive components of the impedance under test. for example, it is a very common misconception to assume that if a user is analyzing a series rc circuit, the real value stored in register address 0x94 and register address 0x95 and the imaginary value stored at register address 0x96 and register address 0x97 correspond to the resistance and capacitive reactance, respectfully. however, this is incorrect because the magnitude of the impedance (|z|) can be calculated by calculating the magnitude of the real and imaginary compo- nents of the dft given by the following formula: 22 ir magnitude += after each measurement, multiply it by the calibration term and invert the product. the magnitude of the impedance is, therefore, given by the following formula: magnitude factorgain impedance = 1 where gain factor is given by magnitude impedance code admittance factorgain ? ? ? ? ? ? ? ? = ? ? ? ? ? ? = 1 the user must calibrate the ad5933 system for a known impedance range to determine the gain factor before any valid measurement can take place. therefore, the user must know the impedance limits of the complex impedance (z unknown ) for the sweep frequency range of interest. the gain factor is determined by placing a known impedance between the input/output of the ad5933 and measuring the resulting magnitude of the code. the ad5933 system gain settings need to be chosen to place the excitation signal in the linear region of the on-board adc. because the ad5933 returns a complex output code made up of real and imaginary components, the user can also calculate the phase of the response signal through the ad5933 signal path. the phase is given by the following formula: phase (rads) = tan ?1 (i / r ) (3) the phase measured by equation 3 accounts for the phase shift introduced to the dds output signal as it passes through the internal amplifiers on the transmit and receive side of the ad5933 along with the low-pass filter and also the impedance connected between the vout and vin pins of the ad5933. the parameters of interest for many users are the magnitude of the impedance (|z unknown |) and the impedance phase (z?). the measurement of the impedance phase (z?) is a two step process. the first step involves calculating the ad5933 system phase. the ad5933 system phase can be calculated by placing a resistor across the vout and vin pins of the ad5933 and calculating the phase (using equation 3) after each measure- ment point in the sweep. by placing a resistor across the vout and vin pins, there is no additional phase lead or lag introduced to the ad5933 signal path and the resulting phase is due entirely to the internal poles of the ad5933, that is, the system phase. once the system phase has been calibrated using a resistor, the second step involves calculating the phase of any unknown impedance by inserting the unknown impedance between the vin and vout terminals of the ad5933 and recalculating the new phase (including the phase due to the impedance) using the same formula. the phase of the unknown impedance (z?) is given by the following formula: ) (? system unknown z ? ? = where: system ? is the phase of the system with a calibration resistor connected between vin and vout. unknown is the phase of the system with the unknown impedance connected between vin and vout. z ? is the phase due to the impedance, that is, the impedance phase. note that it is possible to calculate the gain factor and to calibrate the system phase using the same real and imaginary component values when a resistor is connected between the vout and vin pins of the ad5933, for example, measuring the impedance phase (z?) of a capacitor. the excitation signal current leads the excitation signal voltage across a capacitor by ?90 degrees. therefore, an approximate ?90 degree phase difference exists between the system phase responses measured with a resistor and that of the system phase responses measured with a capacitive impedance. as previously outlined, if the user would like to determine the phase angle of capacitive impedance (z?), the user first has to determine the system phase response ( ) and subtract this from the phase calculated with the capacitor connected between vout and vin (unknown). system ?
ad5933 rev. c | page 22 of 44 in the first quadrant. the standard angle is the angle taken counterclockwise from the positive real x-axis. if the sign of the real component is positive and the sign of the imaginary component is negative, that is, the data lies in the second quadrant, then the arctangent formula returns a negative angle and it is necessary to add a further 180 degrees to calculate the correct standard angle. likewise, when the real and imaginary components are both negative, that is, when the coordinates lie in the third quadrant, then the arctangent formula returns a positive angle and it is necessary to add 180 degrees from the angle to return the correct standard phase. finally, when the real component is positive and the imaginary component is negative, that is, the data lies in the fourth quadrant, then the arctangent formula returns a negative angle. it is necessary to add 360 degrees to the angle to calculate the correct phase angle. a plot showing the ad5933 system phase response calculated using a 220 k calibration resistor (r fb = 220 k, pga = 1) and the repeated phase measurement with a 10 pf capacitive impedance is shown in figure 32 . one important point to note about the phase formula used to plot figure 32 is that it uses the arctangent function that returns a phase angle in radians and, therefore, it is necessary to convert from radians to degrees. 200 180 160 140 120 100 80 60 40 20 0 0 15k 30k 45k 60k 75k 90k 105k 120k frequency (hz) system phase (degrees) 05324-032 220k ? resistor 10pf capacitor therefore, the correct standard phase angle is dependent upon the sign of the real and imaginary component and is summa- rized in table 7 . once the magnitude of the impedance (|z|) and the impedance phase angle (z?, in radians) are correctly calculated, it is possible to determine the magnitude of the real (resistive) and imaginary (reactive) component of the impedance (z unknown ) by the vector projection of the impedance magnitude onto the real and imaginary impedance axis using the following formulas: figure 32. system phase response vs. capacitive phase the phase difference (that is, z?) between the phase response of a capacitor and the system phase response using a resistor is the impedance phase of the capacitor, z? (see figure 33 ). the real component is given by ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 15k 30k 45k 60k 75k 90k 105k 120k frequency (hz) phase (degrees) 05324-033 | z real | = | z | cos ( z ?) the imaginary component is given by | z imag | = | z | sin ( z ?) table 7. phase angle real imaginary uadrant phase angle positive positive first s u 180 )/(tan 1 ri positive negative second s u 180 /tan180 1 ri negative negative third s u 180 /tan180 1 ri positive negative fourth s u 180 /tan360 1 ri figure 33. phase response of a capacitor also when using the real and imaginary values to interpret the phase at each measurement point, take care when using the arctangent formula. the arctangent function returns the correct standard phase angle only when the sign of the real and imaginary values are positive, that is, when the coordinates lie
ad5933 rev. c | page 23 of 44 performing a frequency sweep program the ad5933 into power-down mode. place the ad5933 into standby mode. program frequency sweep parameters into relevant registers (1) start frequency register (2) number of increments register (3) frequency increment register read values from real and imaginary data register. program initialize with start frequency command to the control register. after a sufficient amount of settling time has elapsed, program start frequency sweep command in the control register. poll status register to check if the dft conversion is complete. reset: by issuing a reset command to control register the device is placed in standby mode. program the increment frequency or the repeat frequency command to the control register. y y y n n poll status register to check if frequency sweep is complete. 05324-034 figure 34. frequency sweep flow chart
ad5933 rev. c | page 24 of 44 register map table 8. register name register data function 0x80 control d15 to d8 read/write 0x81 d7 to d0 read/write 0x82 start frequency d23 to d16 read/write 0x83 d15 to d8 read/write 0x84 d7 to d0 read/write 0x85 frequency increment d23 to d16 read/write 0x86 d15 to d8 read/write 0x87 d7 to d0 read/write 0x88 number of increments d15 to d8 read/write 0x89 d7 to d0 read/write 0x8a number of settling time cycles d15 to d8 read/write 0x8b d7 to d0 read/write 0x8f status d7 to d0 read only 0x92 temperature data d15 to d8 read only 0x93 d7 to d0 read only 0x94 real data d15 to d8 read only 0x95 d7 to d0 read only 0x96 imaginary data d15 to d8 read only 0x97 d7 to d0 read only control register (register address 0x80, register address 0x81) the ad5933 has a 16-bit control register (register address 0x80 and register address 0x81) that sets the ad5933 control modes. the default value of the control register upon reset is as follows: d15 to d0 reset to 0xa000 upon power-up. the four msbs of the control register are decoded to provide control functions, such as performing a frequency sweep, powering down the part, and controlling various other functions defined in the control register map. the user may choose to write only to register address 0x80 and not to alter the contents of register address 0x81. note that the control register should not be written to as part of a block write command. the control register also allows the user to program the excitation voltage and set the system clock. a reset command to the control register does not reset any programmed values associated with the sweep (that is, start frequency, number of increments, frequency increment). after a reset command, an initialize with start frequency command must be issued to the control register to restart the frequency sweep sequence (see figure 34 ). table 9. control register map (d15 to d12) d15 d14 d13 d12 function 0 0 0 0 no operation 0 0 0 1 initialize with start frequency 0 0 1 0 start frequency sweep 0 0 1 1 increment frequency 0 1 0 0 repeat frequency 1 0 0 0 no operation 1 0 0 1 measure temperature 1 0 1 0 power-down mode 1 0 1 1 standby mode 1 1 0 0 no operation 1 1 0 1 no operation table 10. control register map (d10 to d9) d10 d9 range no. output voltage range 0 0 1 2.0 v p-p typical 0 1 4 200 mv p-p typical 1 0 3 400 mv p-p typical 1 1 2 1.0 v p-p typical
ad5933 rev. c | page 25 of 44 table 11. control register map (d11, d8 to d0) bits description d11 no operation d8 pga gain; 0 = 5, 1 = 1 d7 reserved; set to 0 d6 reserved; set to 0 d5 reserved; set to 0 d4 reset d3 external system clock; set to 1 internal system clock; set to 0 d2 reserved; set to 0 d1 reserved; set to 0 d0 reserved; set to 0 control register decode initialize with start frequency this command enables the dds to output the programmed start frequency for an indefinite time. it is used to excite the unknown impedance initially. when the output unknown impedance has settled after a time determined by the user, the user must initiate a start frequency sweep command to begin the frequency sweep. start frequency sweep in this mode the adc starts measuring after the programmed number of settling time cycles has elapsed. the user has the ability to program an integer number of output frequency cycles (settling time cycles) to register address 0x8a and register address 0x8b before the commencement of the measurement at each frequency point (see figure 34 ). increment frequency the increment frequency command is used to step to the next frequency point in the sweep. this usually happens after data from the previous step has been transferred and verified by the dsp. when the ad5933 receives this command, it waits for the programmed number of settling time cycles before beginning the adc conversion process. repeat frequency the ad5933 has the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register . this has the benefit of allowing the user to average successive readings. measure temperature the measure temperature command initiates a temperature reading from the part. the part does not need to be in power- up mode to perform a temperature reading. the block powers itself up, takes the reading, and then powers down again. the temperature reading is stored in a 14-bit, twos complement format at register address 0x92 and register address 0x93. power-down mode the default state on power-up of the ad5933 is power-down mode. the control register contains the code 1010,0000,0000,0000 (0xa000). in this mode, both the vout and vin pins are connected internally to gnd. standby mode this mode powers up the part for general operation; in standby mode the vin and vout pins are internally connected to ground. output voltage range the output voltage range allows the user to program the excitation voltage range at vout. pga gain the pga gain allows the user to amplify the response signal into the adc by a multiplication factor of 5 or 1. reset a reset command allows the user to interrupt a sweep. the start frequency, number of increments, and frequency increment register contents are not overwritten. an initialize with start frequency command is required to restart the frequency sweep command sequence. start frequency re gister (register address 0x82, register address 0x83, register address 0x84) the default value of the start frequency register upon reset is as follows: d23 to d0 are not reset on power-up. after a reset command, the contents of this register are not reset. the start frequency register contains the 24-bit digital represen- tation of the frequency from where the subsequent frequency sweep is initiated. for example, if the user requires the sweep to start from frequency 30 khz (using a 16.0 mhz clock), then the user programs the value of 0x0f to register address 0x82, the value of 0x5c to register address 0x83, and the value of 0x28 to register address 0x84. this ensures the output frequency starts at 30 khz. the code to be programmed to the start frequency register is 28c5f0x02 4 mhz16 khz30 27 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? =
ad5933 rev. c | page 26 of 44 frequency increment register (register address 0x85, register address 0x86, register address 0x87) this register determines the number of frequency points in the frequency sweep. the number of points is represented by a 9-bit word, d8 to d0. d15 to d9 are dont care bits. this register, in conjunction with the start frequency register and the increment frequency register, determines the frequency sweep range for the sweep operation. the maximum number of increments that can be programmed is 511. the default value upon reset is as follows: d23 to d0 are not reset on power-up. after a reset command, the contents of this register are not reset. the frequency increment register contains a 24-bit represen- tation of the frequency increment between consecutive frequency points along the sweep. for example, if the user requires an increment step of 10 hz using a 16.0 mhz clock, the user should program the value of 0x00 to register address 0x85, the value of 0x01 to register address 0x86m, and the value of 0x4f to register address 0x87. number of settling time cycles register (register address 0x8a, register address 0x8b) the default value upon reset is as follows: d10 to d0 are not reset on power-up. after a reset command, the contents of this register are not reset (see table 13 ). the formula for calculating the increment frequency is given by this register determines the number of output excitation cycles that are allowed to pass through the unknown impedance, after receipt of a start frequency sweep, increment frequency, or repeat frequency command, before the adc is triggered to perform a conversion of the response signal. the number of settling time cycles register value determines the delay between a start frequency sweep/increment frequency /repeat frequency command and the time an adc conversion commences. the number of cycles is represented by a 9-bit word, d8 to d0. the value programmed into the number of settling time cycles register can be increased by a factor of 2 or 4 depending upon the status of bits d10 to d9. the five most significant bits, d15 to d11, are dont care bits. the maximum number of output cycles that can be programmed is 511 4 = 2044 cycles. for example, consider an excitation signal of 30 khz. the maximum delay between the programming of this frequency and the time that this signal is first sampled by the adc is 511 4 33.33 s = 68.126 ms. the adc takes 1024 samples, and the result is stored as real data and imaginary data in register address 0x94 to register address 0x97. the conversion process takes approximately 1 ms using a 16.777 mhz clock. f00014x02 4 mhz16 hz10 27 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = code increment frequency the user programs the value 0x00 to register address 0x85, the value 0x01 to register address 0x86, and the value 0x4f to register address 0x87. number of increments register (register address 0x88, register address 0x89) the default value upon reset is as follows: d8 to d0 are not reset on power-up. after a reset command, the contents of this register are not reset. table 12. number of increments register reg bits description function format 0x88 d15 to d9 dont care read or write integer number stored in binary format d8 number of increments read or write 0x89 d8 to d0 number of increments read or write integer number stored in binary format table 13. number of settling times cycles register register bits description function format 0x8a d15 to d11 dont care read or write integer number stored in binary format d10 to d9 2-bit decode d10 d9 description 0 0 default 0 1 no. of cycles 2 1 0 reserved 1 1 no. of cycles 4 d8 msb number of settling time cycles 0x8b d7 to d0 number of settling time cycles read or write
ad5933 rev. c | page 27 of 44 status register (register address 0x8f) the status register is used to confirm that particular measure- ment tests have been successfully completed. each of the bits from d7 to d0 indicates the status of a specific functionality of the ad5933. bit d0 and bit d4 to bit d7 are treated as dont care bits these bits do not indicate the status of any measurement. the status of bit d1 indicates the status of a frequency point impedance measurement. this bit is set when the ad5933 has completed the current frequency point impedance measurement. this bit indicates that there is valid real data and imaginary data in register address 0x94 to register address 0x97. this bit is reset on receipt of a start frequency sweep, increment frequency, repeat frequency, or reset command. this bit is also reset on power-up. the status of bit d2 indicates the status of the programmed frequency sweep. this bit is set when all programmed incre- ments to the number of increments register are complete. this bit is reset on power-up and on receipt of a reset command. table 14. status register (register address 0x8f) control word function 0000 0001 valid temperature measurement 0000 0010 valid real/imaginary data 0000 0100 frequency sweep complete 0000 1000 reserved 0001 0000 reserved 0010 0000 reserved 0100 0000 reserved 1000 0000 reserved valid temperature measurement the valid temperature measurement control word is set when a valid temperature conversion is complete indicating that valid temperature data is available for reading at register address 0x92 and register address 0x93. it is reset when a temperature measurement takes place as a result of a measure temperature command having been issued to the control register (register address 0x80 and register address 0x81) by the user. valid real/imaginary data d1 is set when data processing for the current frequency point is finished, indicating real/imaginary data available for reading. d1 is reset when a start frequency sweep/increment frequency/ repeat frequency dds start/increment/repeat command is issued. d1 is reset to 0 when a reset command is issued to the control register. frequency sweep complete d2 is set when data processing for the last frequency point in the sweep is complete. this bit is reset when a start frequency sweep command is issued to the control register. this bit is also reset when a reset command is issued to the control register. temperature data register (16 bitsregister address 0x92, register address 0x93) these registers contain a digital representation of the temper- ature of the ad5933. the values are stored in 16-bit, twos complement format. bit d15 and bit d14 are dont care bits. bit 13 is the sign bit. to convert this number to an actual temperature, refer to the temperature conversion formula section. real and imaginary data registers (16 bitsregister address 0x94, register address 0x95, register address 0x96, register address 0x97) the default value upon reset is as follows: these registers are not reset on power-up or on receipt of a reset command. note that the data in these registers is valid only if bit d1 in the status register is set, indicating that the processing at the current frequency point is complete. these registers contain a digital representation of the real and imaginary components of the impedance measured for the current frequency point. the values are stored in 16-bit, twos complement format. to convert this number to an actual impedance value, the magnitude(real 2 + imaginary 2 )must be multiplied by an admittance/code number (called a gain factor) to give the admittance, and the result inverted to give impedance. the gain factor varies for each ac excitation voltage/gain combination.
ad5933 rev. c | page 28 of 44 serial bus interface control of the ad5933 is carried out via the i 2 c-compliant serial interface protocol. the ad5933 is connected to this bus as a slave device under the control of a master device. the ad5933 has a 7-bit serial bus slave address. when the device is powered up, it has a default serial bus address, 0001101 (0x0d). general i 2 c timing figure 35 shows the timing diagram for general read and write operations using the i 2 c-compliant interface. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (sda), while the serial clock line (scl) remains high. this indicates that a data stream follows. the slave responds to the start condition and shifts in the next 8 bits, consisting of a 7-bit slave address (msb first) plus an r/w bit that determines the direction of the data transferthat is, whether data is written to or read from the slave device (0 = write, 1 = read). the slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is 0, then the master writes to the slave device. if the r/w bit is 1, the master reads from the slave device. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit, which can be from the master or slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to- high transition when the clock is high may be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it may be an instruction telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. because data can flow in only one direction as defined by the r/w bit, it is not possible to send a command to a slave device during a read operation. before performing a read operation, it is sometimes necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10 th clock pulse to assert a stop condition. in read mode, the master device releases the sda line during the low period before the ninth clock pulse, but the slave device does not pull it low. this is known as a no acknowledge. the master then takes the data line low during the low period before the 10 th clock pulse, then high during the 10 th clock pulse to assert a stop condition. 0001101 r/w d7 d6 d5 d4 d3 d2 d1 d0 start condition by master acknowledge by ad5933 slave address byte acknowledge by master/slave s cl sda register address 05324-035 figure 35. timing diagram
ad5933 rev. c | page 29 of 44 writing/reading to the ad5933 s slave address register address register data a wa a p 05324-036 sa waa p pointer command 1011 0000 slave address register address to point to 05324-037 the interface specification defines several different protocols for different types of read and write operations. this section describes the protocols used in the ad5933. the figures in this section use the abbreviations shown in table 1 5 . table 15. i 2 c abbreviation table abbreviation condition s start p stop r read w write a acknowledge a no acknowledge write byte/command byte user command codes the command codes in tabl e 1 6 are used for reading/writing to the interface. they are further explained in this section, but are grouped here for easy reference. table 16. command codes command code code name code description 1010 0000 block write this command is used when writing multiple bytes to the ram; see the block write section. 1010 0001 block read this command is used when reading multiple bytes from ram/memory; see the block read section. 1011 0000 address pointer this command enables the user to set the address pointer to any location in the memory. the data contains the address of the register to which the pointer should be pointing reworded write byte/command byte in this operation, the master device sends a byte of data to the slave device. the write byte can either be a data byte write to a register address or can be a command operation. to write data to a register, the command sequence is as follows (see figure 36 ): 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a register address. 5. the slave asserts an acknowledge on sda. 6. the master sends a data byte. 7. the slave asserts an acknowledge on sda. 8. the master asserts a stop condition on sda to end the transaction. figure 36. writing register data to register address the write byte protocol is also used to set a pointer to an address (see figure 37 ). this is used for a subsequent single- byte read from the same address or block read or block write starting at that address. to set a register pointer, the following sequence is applied: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a pointer command code (see table 16 ; a pointer command = 1011 0000). 5. the slave asserts an acknowledge on sda. 6. the master sends a data byte (a register address to where the pointer is to point). 7. the slave asserts an acknowledge on sda. 8. the master asserts a stop condition on sda to end the transaction. figure 37. setting address pointer to register address block write in this operation, the master device writes a block of data to a slave device (see figure 38 ). the start address for a block write must previously have been set. in the case of the ad5933 this is done by setting a pointer to set the register address. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends an 8-bit command code (1010 0000) that tells the slave device to expect a block write. 5. the slave asserts an acknowledge on sda. 6. the master sends a data byte that tells the slave device the number of data bytes to be sent to it. 7. the slave asserts an acknowledge on sda. 8. the master sends the data bytes. 9. the slave asserts an acknowledge on sda after each data byte. 10. the master asserts a stop condition on sda to end the transaction. aa a a a sw a p slave address block write number bytes write byte 0 byte 1 byte 2 05324-038 figure 38. writing a block write
ad5933 rev. c | page 30 of 44 read operations the ad5933 uses two i 2 c read protocols: receive byte and block read. receive byte in the ad5933, the receive byte protocol is used to read a single byte of data from a register address whose address has previously been set by setting the address pointer. in this operation, the master device receives a single byte from a slave device as follows (see figure 39 ): 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts an acknowledge on sda. 4. t he master receives a data byte. 5. the master asserts a no acknowledge on sda (the slave needs to check that master has received data). 6. the master asserts a stop condition on sda and the transaction ends. sr a a slave address register data p 05324-039 figure 39. reading register data block read in this operation, the master device reads a block of data from a slave device (see figure 40 ). the start address for a block read must previously have been set by setting the address pointer. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a command code (1010 0001) that tells the slave device to expect a block read. 5. the slave asserts an acknowledge on sda. 6. the master sends a byte-count data byte that tells the slave how many data bytes to expect. 7. the slave asserts an acknowledge on sda. 8. the master asserts a repeat start condition on sda. this is required to set the read bit high. 9. the master sends the 7-bit slave address followed by the read bit (high). 10. the slave asserts an acknowledge on sda. 11. the master receives the data bytes. 12. the master asserts an acknowledge on sda after each data byte. 13. a no acknowledge is generated after the last byte to signal the end of the read. 14. the master asserts a stop condition on sda to end the transaction. number bytes read s slave address wa block read aa s slave address r a byte 0 a byte 1 a byte 2 a p 05324-040 figure 40. performing a block read
ad5933 rev. c | page 31 of 44 typical applications measuring small impedances the ad5933 is capable of measuring impedance values up to 10 m if the system gain settings are chosen correctly for the impedance subrange of interest. if the user places a small impedance value (500 over the sweep frequency of interest) between the vout and vin pins, it results in an increase in signal current flowing through the impedance for a fixed excitation voltage in accordance with ohms law. the output stage of the transmit side amplifier available at the vout pin may not be able to provide the required increase in current through the impedance. to have a unity gain condition about the receive side i-v amplifier, the user needs to have a similar small value of feedback resistance for system calibration as outlined in the gain factor setup configuration section. the voltage presented at the vin pin is hard biased at vdd/2 due to the virtual earth on the receive side i-v amplifier. the increased current sink/source requirement placed on the output of the receive side i-v amplifier may also cause the amplifier to operate outside of the linear region. this causes significant errors in subsequent impedance measurements. the value of the output series resistance, r out , (see figure 41 ) at the vout pin must be taken into account when measuring small impedances (z unknown ), specifically when the value of the output series resistance is comparable to the value of the impedance under test (z unknown ). if the r out value is unac- counted for in the system calibration (that is, the gain factor calculation) when measuring small impedances, there is an introduced error into any subsequent impedance measurement that takes place. the introduced error depends on the relative magnitude of the impedance being tested compared to the value of the output series resistance. 05324-048 pga i-v vdd/2 rfb vin ad8531 ad820 ad8641 ad8627 v dd 20k ? 20k ? 1f vdd/2 vout r out r fb dds 2v p- p r1 r2 z unknown transmit side output amplifier figure 41. additional external amplifier circuit for measuring small impedances the value of the output series resistance depends upon the selected output excitation range at vout and has a tolerance from device to device like all discrete resistors manufactured in a silicon fabrication process. typical values of the output series resistance are outlined in table 17 . table 17. output series resistance (r out ) vs. excitation range parameter value (typ) output series resistance value range 1 2 v p-p 200 typ range 2 1 v p-p 2.4 k typ range 3 0.4 v p-p 1.0 k typ range 4 0.2 v p-p 600 typ therefore, to accurately calibrate the ad5933 to measure small impedances, it is necessary to reduce the signal current by attenuating the excitation voltage sufficiently and also account for the r out value and factor it into the gain factor calculation (see the gain factor calculation section). measuring the r out value during device characterization is achieved by selecting the appropriate output excitation range at vout and sinking and sourcing a known current at the pin (for example, 2 ma) and measuring the change in dc voltage. the output series resistance can be calculated by measuring the inverse of the slope (that is, 1/slope) of the resultant i-v plot. a circuit that helps to minimize the effects of the issues previously outlined is shown in figure 41 . the aim of this circuit is to place the ad5933 system gain within its linear range when measuring small impedances by using an additional external amplifier circuit along the signal path. the external amplifier attenuates the peak-to-peak excitation voltage at vout by a suitable choice of resistors (r1 and r2), thereby reducing the signal current flowing through the impedance and minimizing the effect of the output series resistance in the impedance calculations. in the circuit shown in figure 41 , z unknown recognizes the output series resistance of the external amplifier which is typically much less than 1 with feedback applied depending upon the op amp device used (for example, ad820, ad8641, ad8531 ) as well as the load current, bandwidth, and gain.
ad5933 rev. c | page 32 of 44 the key point is that the output impedance of the external amplifier in figure 41 (which is also in series with z unknown ) has a far less significant effect on gain factor calibration and subsequent impedance readings in comparison to connecting the small impedance directly to the vout pin (and directly in series with r out ). the external amplifier buffers the unknown impedance from the effects of r out and introduces a smaller output impedance in series with z unknown . for example, if the user measures z unknown that is known to have a small impedance value within the range of 90 to 110 over the frequency range of 30 khz to 32 khz, the user may not be in a position to measure r out directly in the factory/lab. therefore, the user may choose to add on an extra amplifier circuit like that shown in figure 41 to the signal path of the ad5933. the user must ensure that the chosen external amplifier has a sufficiently low output series resistance over the bandwidth of interest in comparison to the impedance range under test (for an op amp selection guide, see www.analog.com/opamps ). most amplifiers from analog devices have a curve of closed loop output impedance vs. frequency at different amplifier gains to determine the output series impedance at the frequency of interest. the system settings are vdd = 3.3 v vout = 2 v p-p r2 = 20 k r1 = 4 k gain setting resistor = 500 z unknown = 100 pga setting = 1 to attenuate the excitation voltage at vout, choose a ratio of r1/r2. with the values of r1 = 4 k and r2 = 20 k, attenuate the signal by 1/5 th of 2 v p-p = 400 mv. the maximum current flowing through the impedance is 400 mv/ 90 = 4.4 ma. the system is subsequently calibrated using the usual method with a midpoint impedance value of 100 , a calibration resistor, and a feedback resistor at a midfrequency point in the sweep. the dynamic range of the input signal to the receive side of the ad5933 can be improved by increasing the value of the i-v gain resistor at the rfb pin. for example, increasing the i-v gain setting resistor at the rfb pin increases the peak-to-peak signal presented to the adc input from 400 mv (rfb = 100 ) to 2 v p-p (rfb = 500 ). the gain factor calculated is for a 100 resistor connected between vout and vin, assuming the output series resistance of the external amplifier is small enough to be ignored. when biasing the circuit shown in figure 41 , note that the receive side of the ad5933 is hard-biased about vdd/2 by design. therefore, to prevent the output of the external amplifier (attenuated ad5933 range 1 excitation signal) from saturating the receive side amplifiers of the ad5933, a voltage equal to vdd/2 must be applied to the noninverting terminal of the external amplifier.
ad5933 rev. c | page 33 of 44 biomedical: noninvasive blood impedance measurement when a known strain of a virus is added to a blood sample that already contains a virus, a chemical reaction takes place whereby the impedance of the blood under certain conditions changes. by characterizing this effect across different frequencies, it is possible to detect a specific strain of virus. for example, a strain of the disease exhibits a certain characteristic impedance at one frequency but not at another; therefore, the requirement is to sweep different frequencies to check for different viruses. the ad5933, with its 27-bit phase accumulator, allows for subhertz frequency tuning. the ad5933 can be used to inject a stimulus signal through the blood sample via a probe. the response signal is analyzed, and the effective impedance of the blood is tabulated. the ad5933 is ideal for this application because it allows the user to tune to the specific frequency required for each test. probe 2 6 4 adr43x ad5933 top view (not to scale) 10f 0.1f 7v aduc702x top view (not to scale) 1 16 2 15 3 14 4 13 5 6 11 7 10 8 9 rfb 12 05324-041 figure 42. measuring a blood sample for a strain of virus sensor/complex impedance measurement the operational principle of a capacitive proximity sensor is based on the change of a capacitance in an rlc resonant circuit. this leads to changes in the resonant frequency of the rlc circuit, which can be evaluated as shown figure 43 . it is first required to tune the rlc circuit to the area of resonance. at the resonant frequency, the impedance of the rlc circuit is at a maximum. therefore, a programmable frequency sweep and tuning capability is required, which is provided by the ad5933. frequency (hz) proximity impedance ( ? ) resonant frequency change in resonance due to approaching object f o 05324-042 figure 43. detecting a change in resonant frequency an example of the use of this type of sensor is for a train proximity measurement system. the magnetic fields of the train approaching on the track change the resonant frequency to an extent that can be characterized. this information can be sent back to a mainframe system to show the train location on the network. another application for the ad5933 is in parked vehicle detec- tion. the ad5933 is placed in an embedded unit connected to a coil of wire underneath the parking location. the ad5933 outputs a single frequency within the 80 khz to 100 khz frequency range, depending upon the wire composition. the wire can be modeled as a resonant circuit. the coil is calibrated with a known impedance value and at a known frequency. the impedance of the loop is monitored constantly. if a car is parked over the coil, the impedance of the coil changes and the ad5933 detects the presence of the car.
ad5933 rev. c | page 34 of 44 100k 10 0.1 frequency (hz) modulus phase angle 100k 05324-043 ? 75 0 ?50 ?25 1 10 100 1k 10k 100 1k 10k electro-impedance spectroscopy the ad5933 has found use in the area of corrosion monitoring. corrosion of metals, such as aluminum and steel, can damage industrial infrastructures and vehicles such as aircraft, ships, and cars. this damage, if left unattended, may lead to premature failure requiring expensive repairs and/or replacement. in many cases, if the onset of corrosion can be detected, it can be arrested or slowed, negating the requirement for repairs or replacement. at present, visual inspection is employed to detect corrosion; however, this is time consuming, expensive, and cannot be employed in hard-to-access areas. an alternative to visual inspection is automated monitoring using corrosion sensors. monitoring is cheaper, less time consuming, and can be deployed where visual inspections are impossible. electrochemical impedance spectroscopy (eis) has been used to interrogate corrosion sensors, but at present large laboratory test instruments are required. the ad5933 offers an accurate and compact solution for this type of measurement, enabling the development of field deployable sensor systems that can measure corrosion rates autonomously. figure 44. bode plot for aluminum corrosion sensor to make accurate measurements of these values, the impedance needs to be measured over a frequency range of 0.1 hz to 100 khz. to ensure that the measurement itself does not introduce a corrosive effect, the metal needs to be excited with minimal voltage, typically in the 20 mv range. a nearby processor or control unit such as the aduc702x would log a single impedance sweep from 0.1 khz to 100 khz every 10 minutes and download the results back to a control unit. to achieve system accuracy from the 0.1 khz to 1 khz range, the system clock needs to be scaled down from the 16.776 mhz nominal clock frequency to 500 khz, typically. the clock scaling can be achieved digitally using an external direct digital synthesizer like the ad9834 as a programmable divider, which supplies a clock signal to mclk and which can be controlled digitally by the nearby microprocessor. mathematically, the corrosion of aluminum is modeled using an rc network that typically consists of a resistance, r s , in series with a parallel resistor and capacitor, r p and c p . a system metal would typically have values as follows: r s is 10 to 10 k, r p 1 is k to 1 m, and c p is 5 f to 70 f. figure 44 shows a typical bode plot, impedance modulus, and phase angle vs. frequency, for an aluminum corrosion sensor.
ad5933 rev. c | page 35 of 44 choosing a reference for the ad5933 to achieve the best performance from the ad5933, carefully choose the precision voltage reference. the ad5933 has three reference inputs: avdd1, avdd2, and dvdd. it is recom- mended that the voltage on these reference inputs be run from the same voltage supply. there are four sources of error that should be considered when choosing a voltage reference for high accuracy applications: initial accuracy, ppm drift, long-term drift, and output voltage noise. to minimize these errors, a reference with high initial accuracy is preferred. also, choosing a reference with an output trim adjustment, such as a device in the adr43x family, allows a system designer to trim system errors by setting a reference voltage to a voltage other than the nominal. the trim adjust- ment can also be used at temperature to trim out any error. because the supply current required by the ad5933 is extremely low, the parts are ideal for low supply applications. the adr395 voltage reference is recommended in this case. the adr395 requires less than 100 a of quiescent current. it also provides very good noise performance at 8 v p-p in the 0.1 hz to 10 hz range. long-term drift is a measure of how much the reference drifts over time. a reference with a tight long-term drift specification ensures that the overall solution remains stable during its entire lifetime. a reference with a tight temperature coefficient speci- fication should be chosen to reduce the temperature dependence of the system output voltage on ambient conditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. choosing a reference with as low an output noise voltage as practical for the system noise resolution required is important. precision voltage references such as the adr433 produce low output noise in the 0.1 hz to 10 hz range. examples of some recommended precision references for use as supplies to the ad5933 are shown in table 18 . table 18. list of precision references for the ad5933 part no. initial accuracy (mv max) output voltage (v) temp . drift (ppm/c max) 0.1 hz to 10 hz noise (v p-p typ) adr433b 1.5 3. 0 3 3.75 adr433a 4 3. 0 10 3.75 adr434b 1.5 4. 096 3 6.25 adr434a 5 4. 096 10 6.25 adr435b 2 5.0 3 8 adr435a 6 5.0 10 8 adr439b 2 4.5 3 7.5 adr439a 5.5 4.5 10 7.5
ad5933 rev. c | page 36 of 44 layout and configuration power supply bypassing and grounding when accuracy is important in a circuit, carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5933 should have separate analog and digital sections, each having its own area of the board. if the ad5933 is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5933. the power supply to the ad5933 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and effective series inductance (esi); common ceramic types of capacitors are suitable. the 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only, and the signal traces are placed on the solder side. however, this is not always possible with a two-layer board.
ad5933 rev. c | page 37 of 44 evaluation board the ad5933 evaluation board allows designers to evaluate the high performance ad5933 impedance converter with minimum effort. the evaluation board interfaces to the usb port of a pc. it is possible to power the entire board from the usb port. the impedance converter evaluation kit includes a populated and tested ad5933 printed circuit board. the eval-ad5933eb kit is shipped with a cd-rom that includes self-installing software. connect the pc to the evaluation board using the supplied cable. the software is compatible with microsoft? windows? 2000 and windows xp. a schematic of the evaluation board is shown in figure 45 and figure 46 . using the evaluation board the ad5933 evaluation board is a test system designed to simplify the evaluation of the ad5933. the evaluation board data sheet is also available with the evaluation board that gives full information on operating the evaluation board. further evaluation information is available from www.analog.com . prototyping area an area is available on the evaluation board for the user to add additional circuits to the evaluation test set. users may want to include switches for multiple calibration use. crystal oscillator (xo) vs. external clock a 16 mhz oscillator is included on the evaluation board. however, this oscillator can be removed and, if required, an external cmos clock can be connected to the part.
ad5933 rev. c | page 38 of 44 schematics 05324-044 figure 45. eval-ad5933ebz usb schematic
ad5933 rev. c | page 39 of 44 05324-045 figure 46. eval-ad5933ebz schematic
ad5933 rev. c | page 40 of 44 05324-046 figure 47. linear regulator on the eval-ad5933eb evaluation board
ad5933 rev. c | page 41 of 44 05324-047 figure 48. decoupling on the eval-ad5933eb evaluation board
ad5933 rev. c | page 42 of 44 bill of materials table 19. reference designator smd part description supplier no. 1 c1, c3, c5 to c9, c11, c15, c16, c 18 to c22, c24, c26 to c28, c32, c34, c36, c37, c39 yes 50 v x7r smd ceramic capacitors, 0.1 f, 0603 fec 1301804 c2, c4, c12 to c14, c25, c30, c31, c33, c38, c40 yes x5r ceramic capacitors, 10 f, 0805 fec 9402136 c10, c17 yes 50 v x7r smd ceramic capacitors, 22 pf, 0603 fec 722-005 c23 yes 6.3 v x5r smd ceramic capacitor, 2.2 f, 0603 fec 9402101 c29, c35 yes 16 v tantalum capacitors, 10 f, cap\taj_b fec 498-737 c41 no wire wrap pin (2), cap-7.5 mm c42 yes 50 v npo smd ceramic capacitor, 15 pf, 0603 fec 721-980 c43 yes 16 v x7r smd ceramic capacitor, 1 f, 0603 fec 1310220 clk1, clk2 no smb sockets, 50 fec 1111349 d4 yes light emitting diode, 0805 fec 1318243 j1 yes usb mini-b connector (usb-otg) fec 9786490 j2 to j6 no connector\power 2-way pin terminal blocks (5 mm pitch) fec 151-789 lk1 to lk14 no jumper blocks, 2-way 0.1" spacing sip-2p fec 1022247/fec 150-411 r1 yes smd resistor 50 , 0603 fec 1170658 r2 no through-hole resistor, insert ed in wire wrap pins, 200 k r1/8wa 2 fec 9341501 r3 3 no 4 k through hole resistors not inserted 4 r4 3 no 20 k through hole resistors not inserted 4 r5, r6 yes smd resistor 100 k, 0603 fec 9330402 r7 yes smd resistor 0 , 0603 fec 9331662 r8, r9 yes smd resistors 2.2 k, 0603 fec 9330810 r10 yes smd resistor 10 k, 0603 fec 9330399 r11 yes smd resistor 1 k, 0805 fec 9332383 r12, r13 yes smd resistors 20 k, 0603 fec 9330771 t1 to t3, t5 to t8 no testpoints fec 8731128 vin, vout no smb sockets 50 fec 1111349 u1 yes op97 op amp so8nb not inserted u2 yes 24lc64 ic serial eeprom 64 kb 2.5 v soic8 so8nb fec 9758070 u3 yes cy7c68013-csp usb microcontroller cypress cy7c68013a-56lfxc lfcsp-56 digi-key 428-1669-nd u4 yes adr433 3 v reference soic-8 adr433arz u5 yes adp3303-3.3 precision low dropout voltage regulator so-8nb adp3303arz-3.3 u6 yes ad5933/34 ssop-16 ad5933yrsz/ad5934yrsz y1 yes xtal-cm309s cm309s smd crystal 24 mhz, xtal_cm309s fec 9509658 y2 yes 3.3 v, 16 mhz clock oscillator ael-4313 stick-on feet 4 fec 651-813 antistatic bag, board to be packed in bag fec 522-764 usb a to mini-b cable digi-key 167-1011-nd 1 fec = farnell electronics. 2 place wire wrap pins into holes and insert a resistor with shortened legs into pins. 3 keep holes for component r3 and component r4 free of solder. 4 insert wire wrap pins into holes.
ad5933 rev. c | page 43 of 44 outline dimensions compliant to jedec standards mo-150-ac 060106-a 16 9 8 1 6.50 6.20 5.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 49. 16-lead shrink small outline package [ssop] (rs-16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad5933yrsz ?40c to +125c 16-lead shrink small outline package (ssop) rs-16 AD5933YRSZ-REEL7 ?40c to +125c 16-lead shri nk small outline package (ssop) rs-16 eval-ad5933ebz ?40c to +125c evaluation board 1 z = rohs compliant part.
ad5933 rev. c | page 44 of 44 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2005C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05324-0-8/10(c)

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